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1 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary general description the EM83040B is a dot matrix lcd driver, which is fabricated by low power cmos technology. this chip includes 80-bits shift register, 80 bits data latch and 80 bits level driver. a lcd ram inside can be mapping to lcd signal. it converts ram data to parallel data and output waveform to lcd. features (1) supply power: 2.5~5.5v (2) lcd drive voltage: 3.6 to15v (3) internal ram: 2.5k x 4 bits (4) ram can be controlled by eight signals including four bits data bus. (5) duty: 1/32, 1/48, 1/64, 1/80 (6) build in dc/dc converter: double, triple, quad and five times. (7) modularized function: connect to another 83040b to extent lcd matrix (8) one dc converter enabled and other 83040b can share with this. (9) internal regulator output for dc/dc converter controlled by control register. (10) chip form (EM83040Bh), 128 pin package (14mm x 20mm EM83040Baq), 160 pin package (EM83040Bbq) (11) bias: 1/5 (32 common), 1/7 (48 common), 1/9 (64 and 80 common) fixed by internal circuit. (12) internal rc clock about 250 khz. application (1) data bank (2) lcd toy (3) education computer
* this specification are subject to be changed without notice. EM83040B lcd controller 2 9.14.2001 preliminary preliminary preliminary preliminary preliminary pin assignments EM83040Baq 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 main m1 m0 en nc nc nc nc ramen ramads ramw ramr ramd3 ramd2 rmad1 ramd0 load vdd gnd vout vss4 vss3 cb ca vss2+ vss2- v1 v2 vreg nc nc nc nc nc v3 v4 v5 o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 o19 o20 o21 o22 o23 o24 o25 o26 o53 o52 o51 nc nc nc nc nc o50 o49 o48 o47 o46 o45 o44 o43 o42 o41 o40 o39 o38 o37 o36 o35 o34 o33 o32 o31 o30 nc nc nc nc nc nc o29 o28 o27 o79 o78 o77 o76 o75 o74 o73 o72 o71 o70 o69 o68 o67 o66 o65 o64 o63 o62 o61 o60 o59 o58 o57 o56 o55 o54 EM83040Baq
3 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary EM83040Bbq EM83040Bbq vss4 vss3 + - vreg vout
* this specification are subject to be changed without notice. EM83040B lcd controller 4 9.14.2001 preliminary preliminary preliminary preliminary preliminary block diagram vreg v1 reg(5~0) bias mux : : : : : m1,m0 buffer1 buffer2 buffer3 buffer4 buffer5 regulator ir(2~0) resistance ratio vout vss4 vss3 ca cb vss2+ vss2-
5 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary pin descriptions symbol i/o function vdd power system power supply gnd power ground vout power voltage converter input/output pin connect this pin to gnd through capacitor en=1,vout=vdd vss4 power step-up capacitor en=1, vss4=vdd vss3 power step-up capacitor en=1, vss3=vdd vss2+ power step-up capacitor en=1, vss2=vdd vss2- power step-up capacitor vreg power output voltage regulator terminal. provides the voltage between v1 and gnd through a resistive voltage divider. main i master or slave control signal. main=1, master unit main=0, slave unit en i this pin control whole chip power. this chip will work when this pin is connected to ground. and whole chip will disable when connect to vdd voltage. en=0 and main=1 the chip will generate vss2+, vss2- vss3, vss4, vout, load signal and internal rc clock. en=1, standby mode m1 i mode select m0 i mode select ramen ram read and write control signal. 1 => can not read and write. 0=> can read and write. ramads ram data select signal 1=> ram data, 0=>address ramw ram write signal, low write ramr ram read signal, low read ramd3~ram ram data or address bus d0 load i/o lcd load signal between one common signal to another. main=1, the master unit will output load signal. main=0, the slave will accept the signal from master unit. ca i coupling capacitor cb i coupling capacitor v1~v5 i reference voltage input, highest v1 k lowest v5 o1~o80 o lcd waveform output
* this specification are subject to be changed without notice. EM83040B lcd controller 6 9.14.2001 preliminary preliminary preliminary preliminary preliminary function descriptions (1)user can use main pin to chose master unit or slave unit. main unit function 1 master generate these signals: load, ca, cb, vss2+, vss2-, vss3, vss4, vout internal rc clock 0 slave accept these master unit signals load, vout, v1, v2, v3, v4, v5 no internal rc clock (2)user can use m1,m2 to choose four modes. as followed master main m1 m0 segment common bias mode1 1 0 0 o(16:1)=s(16:1) o(80:17)=c(64:1) 1/9 mode2 1 0 1 o(80:1)=c(80:1) 1/9 mode3 1 1 0 o(32:1)=s(32:1) o(80:33)=c(48:1) 1/7 mode4 1 1 1 o(48:1)=s(48:1) o(80:49)=c(32:1) 1/5 slave main m1 m0 segment common bias mode1 0 0 0 o(80:1)=s(80:1) 1/9 mode2 0 0 1 o(80:1)=s(80:1) 1/9 mode3 0 1 0 o(80:1)=s(80:1) 1/7 mode4 0 1 1 o(80:1)=s(80:1) 1/5 * s=segment, c=common * (m1, m0) for master must same as slave unit (3)ram control write mode fig. 3 lcd ram can be written or read with control signal. the ramen pin can select a ram which can be read or write. the ramads pin can select whether
7 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary ramd(3:0) are data or address of ram. at the address mode, ramads is low and user should sent address three times, from address (11:8) to address (3:0). then it will go into data mode when ramads is high. in data mode, user can sent one or more nibble data which address can be increased by internal counter. once the ramen pin is high, the ram can not read and write. (4)read control ramen ramads ramd(3:0) ramw ramr a3 a2 a1 d1 d2 d3 ram enable ram disable address data a3=address (11:8) a2=address(7:4) a1=address(3:0) ten tdv tdh tdd fig. 4 as same as write mode, user has to sent address three times. and read data from ram one by one which address can be increased by internal counter. note!! be sure to make ramr low pulse 2us (tdv +data) width and 2us (tdd) high width at least. (5) ram mapping ram address is from 0 to address 2562 user fill ??to lcd ram, lcd driver will generate ?ight?waveform. otherwise, it will generate a ?ark waveform. the lcd ram area is mapped to segment 1 to segment 80 from address 0 to address 19. and user can refer to fig.5 and table 1 to get the idea of lcd ram mapping. the other ram can use as general ram for data storage if not mapping to lcd display. and the ram of address 2560, 2561 and 2562 is control registers. table 1: lcd mapping ram area common segment master/slave display area 32 48 master 1,2,3 32 80 slave 1,2,3,4 48 32 master 1,2,5,6 48 80 slave 1,2,3,4,5,6,7 64 16 master 1,5,8 64 80 slave 1,2,3,4,5,6,7,8,9 80 0 master no mapping ram 80 80 slave 1,2,3,4,5,6,7,8,9,10 any any any area 11 is general ram
* this specification are subject to be changed without notice. EM83040B lcd controller 8 9.14.2001 preliminary preliminary preliminary preliminary preliminary fig.5 as same as write mode , user has to sent address three times. and read data from ram one by one which address can be increased by internal counter. note!! be sure to make ramr low pulse 2 s (tdv+data) width and 2 s (tdd) high width at least. (5) ram mapping ram address is from 0 to address 2559 user fill ??to lcd ram , lcd driver will generate ?ight?waveform. otherwise , it will generate a ?ark?waveform. the lcd ram area is mapped to segment 1 to segment 80 from address 0 to address 19. and user can refer to fig.5 to get the idea of lcd ram mapping. the other ram can use as general ram for data storage. and the ram of address 2560 is a control register. address2559 ................... address0031 ................... address0063 ................... address0051 ................... ..................................... .......................... address1023 ................... address1535 ................... address2047 ................... address2547 ................................................................................................................... ...... address2528 address2035 ......................................................................................address2019...............add ress2016 address1523 ............................................................address1511........................................addr ess1504 address1011 .......................address1003 ............................................................................. ad dress0992 lcd ram area 10 area 11 area 9 area 8 area 5 area 6 area 7 area 4 area 3 area 2 area 1 address 2560,2561 2562 control register address 2560,2561,2562 control register empty area : : : : : : : : : : : : : : : : ................................... address0032 address0019 ................... b3 b2 b1 b0 ................... s80s79s78s77 s4 s3 s2 s1 s48 s32 s16 address0011................ address7........... address0003............... address0000 com80 com64 com48 com32 com2 com1 b3 b2 b1 b0
9 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary (6) lcd waveform fig.6 v1 v2 v3 v4 v5 gnd v1 v2 v3 v4 v5 gnd v1 v2 v3 v4 v5 gnd v1 v2 v3 v4 v5 gnd v1 v2 v3 v4 v5 gnd frame com0 com1 com2 seg seg light dark
* this specification are subject to be changed without notice. EM83040B lcd controller 10 9.14.2001 preliminary preliminary preliminary preliminary preliminary ( 7) control register address bit3 bit2 bit1 bit0 2560 irs ir2 ir1 ir0 2561 reg3 reg2 reg1 reg0 2562 ps1 ps0 reg5 reg4 x: don t care default status of address 2560,2561 and 2562, respectively: 0010, 0000, 0000 address 2562 bit3~2(ps1, ps0) be selected: use settings ps1 ps0 step-up v v/f external circuit regulator circuit voltage input circuit only the internal power supply is used 1 1 oox only the v regulator circuit and the v/f circuit 1 0 x o o vout are used only the v/f circuit is used 0 1 x x o v1 only the external power supply is used 0 0 x x x v1 to v5 address 2562 bit1~0 and 2561 bit3~0 (reg5~reg0) is selected the vev value reg5~reg0 v ev v ev step 000000 1.2 v 000001 1.212 v 011111 1.572 v 0.012v 100000 1.584 v 111110 1.944 v 111111 1.956 v v 1 r a r b v reg v ev vout fig.7
11 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary address 2560 bit3 (irs) is internal resistor selected irs=0: internal regulator resistor is used. irs=1: internal regulator resistor is not used. (external resistor is used) address 2560 bit0~2(ir2, ir1, ir0) is selected for the v1 voltage regulator internal resistance ratio ir2~ir0 resistor ratio (1+rb/ra) 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 1 0 0 5.0 1 0 1 5.5 1 1 0 6.0 1 1 1 6.5 the v1 voltage can be calculated using equation a over the range where vdd < v1 vout v1=(1+rb/ra) v ev *(94%~97%) (equation a) (94%~97%) depend on loading example: default: irs=0 (internal regulator resistor is used), (ir2, ir1, ir0)=(0, 1, 0), and (reg5~0)=(000000) v1=(1+rb/ra) v ev *(94%~97%)=4.0 1.2*(94%~97%)= 4.51 v~4.65v when irs=0 (internal regulator resistor is used), (ir2, ir1, ir0)=(0, 1, 1), and (reg5~0)=(100000) v1=(1+rb/ra) v ev *(94%~97%)=4.5 1.584*(94%~97%)= 6.7~6.91 v fig. 8 show the v1 voltage measured by values of the internal resistance ratio resistor (1+rb/ra) for v1 voltage adjustment and electric volume resister (reg5~reg0). fig. 8 the output voltage v1 is determined by function of the v1 voltage regulator ratio register (1+rb/ra), and the electric volume resister (reg5~reg0). (8) the step-up voltage circuit case of the double step-up, the triple step-up and case of the quad step-up vout is output voltage pin the bias voltage v1 is supported from vreg. (a) double step-up, (b) triple step-up, (c) quad step-up (d) five times step-up c1=0.47 to 1.0gf, c2=1.0 to 4.7uf (a) vout=2*vdd (b) vout=3*vdd (c) vout=4*vdd (d) vout=5*vdd fig. 9 EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c2 c2 c1 c2 c2 c2 c1 EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c2 c2 c2 c2 c1 EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c2 c2 c2 c2 c1 EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c2
* this specification are subject to be changed without notice. EM83040B lcd controller 12 9.14.2001 preliminary preliminary preliminary preliminary preliminary (9) reference circuit examples are as following fig. 10 (a) only the internal power supply is used, control register (ps1, ps0, irs)=(1,1,0) (b) only the internal power supply is used, control register (ps1, ps0, irs)=(1,1,1) when internal regulator resistor is not used (external resistor is used), v1=vreg*(1+rb /ra ) (c) only the v regulator circuit and the v/f circuit are used, control register (ps1, ps0, irs)=(1,0,0) (d) only the v regulator circuit and the v/f circuit are used, control register (ps1, ps0, irs)=(1,0,1), when internal regulator resistor is not used (external resistor is used), v1=vreg*(1+rb /ra ) (e) only the v/f circuit is used, control register (ps1, ps0)=(0,1) (f) only the external power supply is used, control register (ps1, ps0)=(0,0) EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c2 c2 c2 c2 c1 main vdd EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c2 c2 c2 c2 c1 rb ra main vdd EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c1 external power supply main vdd EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c1 rb ra external power supply vdd EM83040B vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 c1 external power supply vdd EM83040B vout vss4 vss3 ca cb vss2+ vss2- vreg v1 v2 v3 v4 v5 external power supply vdd (a) (b) (c) (d) (e) (f) fig. 10
13 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary absolute maximum ratings rating symbol value unit dc supply voltage vdd <3.5 v input voltage vin -0.5 to vdd 0.5 v operating temperature range ta - 30 to 8 0 c step-up voltage vout <18 v ac electrical characteristics (t a = - 3 0 c ~ 8 0 c, v dd =3v v s s =0v) parameter sym. min. typ. max. unit rc clock variable vrc -20 +20 % frame period tframe 1/64 s load period tload 31 s enable time ten 30 s write low pulse tw 2 s data hold time tdh 500 ns data to data time tdd 2 s data valid time tdv 1500 ns dc electrical characteristics (t a = - 3 0 c ~ 8 0 c, v dd =3 v 5%, v s s =0v) parameter sym. min. typ. max. unit condition input voltage v dd 2.5 5.5 with double step-up 2.5 5.5 with triple step-up 2.5 4.0 with quad step-up 2.5 3.3 with five times step-up output low current i ol -100 av dd =3v standby current i sd 14 a en=1 operating voltage i op 180 220 a en=0, main =1(master) , dc converter enable, five times step-up (m1, m0)=(1,1) v1=11v, 250khz clock, no load 40 70 a en=0 . main =0 (slave) ,dc converter enable, five times step-up (m1, m0)=(1,1) v1=11v, 250khz clock, no load current of a buffer (v1 tov5) ibuf 4 6 10 a current of a buffer voltage variation of regulator vreg v-0.1 v v+0.1 v regulator current ireg 10 15 a bias resister r_bias 1800 2000 2200 k ? v
* this specification are subject to be changed without notice. EM83040B lcd controller 14 9.14.2001 preliminary preliminary preliminary preliminary preliminary ac timing fig .11 lcd control timing lcd control timing fig .12 lcd ram write mode frame load s0 s1 s2 s3 sn c0 c1 cm c0 positive frame negative frame tframe tload en ramen ramads ramd(3:0) ramw ramr a3 a2 a1 d1 d2 d3 ram enable ram disable address data a3=address(11:8) a2=address(7:4) a1=address(3:0) tw tdh ten tdd
15 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary fig .13 lcd ram read mode application circuit (1) c32 x s48 fig .14 ramen ramads ramd(3:0) ramw ramr a3 a2 a1 d1 d2 d3 ram enable ram disable address data a3=address (11:8) a2=address(7:0) a1=address(3:0) d1= first nibble d2=second nibble d3=third nibble data ten tdv tdh tdd vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 nc nc vdd vdd vdd
* this specification are subject to be changed without notice. EM83040B lcd controller 16 9.14.2001 preliminary preliminary preliminary preliminary preliminary (2) c32 x s128 fig .15 (3) c48 x s112 fig .16 vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc vdd vdd vdd s127 ...... s80 vout c31 : : c0 master vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc nc nc nc nc nc nc vss vdd vdd s79 ...... s0 vout slave connect to master chip lcd 32*128 vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc vdd vdd gnd s111 ...... s80 vout c47 : : c0 master vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc nc nc nc nc nc nc vss vdd gnd s79 ...... s0 vout slave connect to master chip lcd 48*112
17 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary (4) c64 x s96 fig .17 vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc vdd gnd gnd s95 ...... s80 vout c63 : : c0 master vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc nc nc nc nc nc nc vss gnd gnd s79 ...... s0 vout slave connect to master chip lcd 64*96
* this specification are subject to be changed without notice. EM83040B lcd controller 18 9.14.2001 preliminary preliminary preliminary preliminary preliminary (5) c80 x s160 fig .18 vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc vdd gnd gnd vout c79 : : c0 master vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc nc nc nc nc nc nc vss gnd vdd s79 ...... s0 vout slave1 connect to master chip vdd gnd main m1 m0 en ramen ramads ramw ramr ramd(3:0) load vout vss4 vss3 cb ca vss2+ vss2- vreg v1 v2 v3 v4 v5 load nc nc nc nc nc nc nc vss gnd vdd s159 ...... s80 vout slave2 connect to master chip lcd 80*160
19 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary pad diagram chip size : 3890 m x 2500 m pad no. sym. x y 1 main -1370.0 1120.0 2 m1 -1480.0 1120.0 3 m0 -1590.0 1120.0 4 enb(en) -1700.0 1120.0 5 6 7 8 9 ramenb(ramen) -1820.0 1065.0 10 ramads -1820.0 955.0 11 ramw -1820.0 845.0 12 ramr -1820.0 735.0 13 ramd_3_ -1820.0 630.0 14 ramd_2_ -1820.0 525.0 15 ramd_1_ -1820.0 420.0 16 ramd_0_ -1820.0 315.0 17 load -1820.0 210.0 18 vdd -1820.0 105.0 20 gnd -1820.0 0.0 (0,0) 1 main 2 m1 3 m0 4 enb 9 ramenb 10 ramads 11 ramw 12 ramr 13 ramd_3_ 14 ramd_2_ 15 ramd_1_ 16 ramd_0_ 17 load 18 vdd 19 gnd 20 vout 21 vss4 22 vss3 23 cb 24 ca 25 vss2a 26 vss2b 27 vv1 28 v2 29 vreg 35 v3 36 v4 37 v5 38 op_0_ 39 op_1_ 40 op_2_ 41 op_3_ 42 op_4_ 43 op_5_ 44 op_6_ 45 op_7_ 46 op_8_ 47 op_9_ 48 op_10_ 49 op_11_ 50 op_12_ 51 op_13_ 52 op_14_ 53 op_15_ 54 op_16_ 55 op_17_ 56 op_18_ 57 op_19_ 58 op_20_ 59 op_21_ 60 op_22_ 61 op_23_ 62 op_24_ 63 op_25_ 64 op_26_ 65 op_27_ 66 op_28_ 67 op_29_ 74 op_30_ 75 op_31_ 76 op_32_ 77 op_33_ 78 op_34_ 79 op_35_ 80 op_36_ 81 op_37_ 82 op_38_ 83 op_39_ 84 op_40_ 85 op_41_ 86 op_42_ 87 op_43_ 88 op_44_ 89 op_45_ 90 op_46_ 91 op_47_ 92 op_48_ 93 op_49_ 94 op_50_ 100 op_51_ 101 op_52_ 102 op_53_ 103 op_54_ 104 op_55_ 105 op_56_ 106 op_57_ 107 op_58_ 108 op_59_ 109 op_60_ 110 op_61_ 111 op_62_ 112 op_63_ 113 op_64_ 114 op_65_ 115 op_66_ 116 op_67_ 117 op_68_ 118 op_69_ 119 op_70_ 120 op_71_ 121 op_72_ 122 op_73_ 123 op_74_ 124 op_75_ 125 op_76_ 126 op_77_ 127 op_78_ 128 op_79_
* this specification are subject to be changed without notice. EM83040B lcd controller 20 9.14.2001 preliminary preliminary preliminary preliminary preliminary pad no. sym. x y 21 vss4 -1820.0 -210.0 22 vss3 -1820.0 -315.0 23 cb -1820.0 -420.0 24 ca -1820.0 -525.0 25 vss2a(vss2+) -1820.0 -630.0 26 vss2b(vss2-) -1820.0 -735.0 27 vv1(v1) -1820.0 -845.0 28 v2 -1820.0 -955.0 29 vreg -1820.0 -1065.0 30 31 32 33 34 35 v3 -1700.0 -1120.0 36 v4 -1590.0 -1120.0 37 v5 -1480.0 -1120.0 38 op_0_ -1370.0 -1120.0 39 op_1_ -1265.0 -1120.0 40 op_2_ -1160.0 -1120.0 41 op_3_ -1055.0 -1120.0 42 op_4_ -950.0 -1120.0 43 op_5_ -845.0 -1120.0 44 op_6_ -740.0 -1120.0 45 op_7_ -635.0 -1120.0 46 op_8_ -530.0 -1120.0 47 op_9_ -425.0 -1120.0 48 op_10_ -320.0 -1120.0 49 op_11_ -215.0 -1120.0 50 op_12_ -110.0 -1120.0 51 op_13_ -5.0 -1120.0 52 op_14_ 100.0 -1120.0 53 op_15_ 205.0 -1120.0 54 op_16_ 310.0 -1120.0 55 op_17_ 415.0 -1120.0 56 op_18_ 520.0 -1120.0 57 op_19_ 625.0 -1120.0 58 op_20_ 730.0 -1120.0 59 op_21_ 835.0 -1120.0 60 op_22_ 940.0 -1120.0 61 op_23_ 1045.0 -1120.0 62 op_24_ 1150.0 -1120.0 63 op_25_ 1255.0 -1120.0 64 op_26_ 1365.0 -1120.0 65 op_27_ 1475.0 -1120.0
21 * this specification are subject to be changed without notice. 9.14.2001 EM83040B lcd controller preliminary preliminary preliminary preliminary preliminary pad no. sym. x y 66 op_28_ 1585.0 -1120.0 67 op_29_ 1695.0 -1120.0 68 69 70 71 72 73 74 op_30_ 1820.0 -1065.0 75 op_31_ 1820.0 -955.0 76 op_32_ 1820.0 -845.0 77 op_33_ 1820.0 -735.0 78 op_34_ 1820.0 -630.0 79 op_35_ 1820.0 -525.0 80 op_36_ 1820.0 -420.0 81 op_37_ 1820.0 -315.0 82 op_38_ 1820.0 -210.0 83 op_39_ 1820.0 -105.0 84 op_40_ 1820.0 0.0 85 op_41_ 1820.0 105.0 86 op_42_ 1820.0 210.0 87 op_43_ 1820.0 315.0 88 op_44_ 1820.0 420.0 89 op_45_ 1820.0 525.0 90 op_46_ 1820.0 630.0 91 op_47_ 1820.0 740.0 92 op_48_ 1820.0 850.0 93 op_49_ 1820.0 960.0 94 op_50_ 1660.0 1115.0 95 96 97 98 99 100 op_51_ 1695.0 1120.0 101 op_52_ 1585.0 1120.0 102 op_53_ 1475.0 1120.0 103 op_54_ 1365.0 1120.0 104 op_55_ 1255.0 1120.0 105 op_56_ 1150.0 1120.0 106 op_57_ 1045.0 1120.0 107 op_58_ 940.0 1120.0 108 op_59_ 835.0 1120.0 109 op_60_ 730.0 1120.0
* this specification are subject to be changed without notice. EM83040B lcd controller 22 9.14.2001 preliminary preliminary preliminary preliminary preliminary pad no. sym. x y 110 op_61_ 625.0 1120.0 111 op_62_ 520.0 1120.0 112 op_63_ 415.0 1120.0 113 op_64_ 310.0 1120.0 114 op_65_ 205.0 1120.0 115 op_66_ 100.0 1120.0 116 op_67_ -5.0 1120.0 117 op_68_ -110.0 1120.0 118 op_69_ -215.0 1120.0 119 op_70_ -320.0 1120.0 120 op_71_ -425.0 1120.0 121 op_72_ -530.0 1120.0 122 op_73_ -635.0 1120.0 123 op_74_ -740.0 1120.0 124 op_75_ -845.0 1120.0 125 op_76_ -950.0 1120.0 126 op_77_ -1055.0 1120.0 127 op_78_ -1160.0 1120.0 128 op_79_ -1265.0 1120.0 * the substrate must be fixed at gnd level or floating, cannot fixed to vdd level.

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